A high-speed operation of a processor in an information processing device is made possible by internally providing the processor with high-speed accessible small-capacity registers, and by executing an arithmetic and logic operation among the register, and by returning results from the arithmetic and logic operations back to the registers to be held therein. The operations of the processor are controlled by instructions so as to sequentially interpret and execute the instructions.
An example of a conventional processor is shown in FIG. 14. The control unit 108 sequentially decodes and executes instructions read from the instruction cache 109. The operation device 102, with its input and output ports being connected to the register file 101, receives input data from a specified registers 105 in accordance with an instruction from the control unit 108 and writes results from the arithmetic and logic operations onto the specified registers 105. Moreover, in some cases, the control unit 108 instructs data to be transferred between the registers 105 and the main memory device 112. In this case, the control unit 108 performs processing of reading data via the load buffer 111 from the main memory device 112 to write the data onto specified registers 105, or data via the store buffer 110 from the registers 105 to write the data onto the main memory device 112.
In a processor, an inter-register copy instruction is often executed in order to create a duplicate value held in a register or to use a value held in a register during the next iteration process or another subroutines. The instruction is for writing the same value as held in a register (source register) onto another register (destination register). The inter-register copy instruction is generally to be inserted and issued by a complier due to a limitation in terms of an architecture and the step of the insertion and issuance is part of time-wasting processing from a user's viewpoint. In the actual operation, an arithmetic and logic operation device is not used and it is therefore desirous that its execution time is reduced to a minimum.